December 11, 2017
Comments Off on Performance Comparison of Pass Transistor and CMOS Logic Configuration based De-Multiplexers
Posted in: IEEE 2017, VLSI
Performance Comparison of Pass Transistor and CMOS Logic Configuration based De-Multiplexers Abstract: This research paper analyzes the performance of De-Multiplexer (De-Mux) using Pass Transistor Logic Configuration (PTLC) and CMOS Logic Configuration (CLC). Furthermore, a comparison between the performances of both the configurations in terms of power dissipation, chip area, power supply and drive current levels […]
December 11, 2017
Comments Off on Online Testing for Three Fault Models in Reversible Circuits
Posted in: IEEE 2017, VLSI
Online Testing for Three Fault Models in Reversible Circuits Abstract: In this paper we propose an approach for the design of online testable reversible circuits. A reversible circuit composed of Toffoli gates can be made online testable by adding two sets of CNOT gates and a single parity line. The performance of the proposed approach […]