December 11, 2017
Comments Off on Ultralow-Energy Variation-Aware Design Adder Architecture Study
Posted in: IEEE 2017, VLSI
Ultralow-Energy Variation-Aware Design: Adder Architecture Study Abstract: Power consumption of digital systems is an important issue in nanoscale technologies and growth of process variation makes the problem more challenging. In this brief, we have analyzed the latency, energy consumption, and effects of process variation on different structures with respect to the design structure and logic […]
December 11, 2017
Comments Off on Using Boolean Tests to Improve Detection of Transistor Stuck-open Faults in CMOS Digital Logic Circuits
Posted in: IEEE 2017, VLSI
Using Boolean Tests to Improve Detection of Transistor Stuck-open Faults in CMOS Digital Logic Circuits Abstract: Currently transistor stuck-open (TSOP) faults in CMOS digital logic circuits are detected by two pattern tests consisting of an initialization pattern to set the output of a faulty gate followed by a pattern that detects a stuck-at fault. Some TSOP […]