An Improved Dynamic Latch Based Comparator for 8-bit Asynchronous SAR ADC

An Improved Dynamic Latch Based Comparator for 8-bit Asynchronous SAR ADC


High speed analog to digital converters (ADC), memory sense amplifiers, RFID applications, data receivers with low power and area efficient designs has attracted a wide variety of dynamic comparators. This paper presents an improved design for a dynamic latch based comparator in achieving higher speed of conversion targeting 8-bit asynchronous successive approximation register (ASAR) ADC. The comparator has two different stages comprising of a dynamic differential input gain stage and an output latch. The objective of improving the speed of conversion is done by removing the dead time required for reset in the differential input stage. In the proposed work the output node in the differential gain stage requires lesser time to regain higher charge potential. The proposed methodology has been designed and simulated using 180nm CMOS technology operated on a single 1V power supply and achieves complete 8-bit conversion in 75nsec.


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