Implementation of high performance SRAM Cell Using Transmission Gate

Implementation of high performance SRAM Cell Using Transmission Gate

Abstract:

Static Random Access Memory (SRAM) plays a most substantial role in the microprocessor world, but as the technology is scaling down in nanometers, leakage parameters and delay are the most common problems for SRAM cell which is basically designed for very low power application. Transmission gate is used to further reduced leakage current penetrating in the 8T SRAM cell. Comparative analysis is performed by using transmission gate. This paper represents a method for design a variability aware SRAM cell. The proposed architecture of the TG8T SRAM cell is analogous to the standard 6T SRAM cell, the only exception is that they possess full transmission gates which replace an access pass transistor. The paper studies the different parameters of TG8Twrite operation at 0.7 V like leakage current is 229.2fA, leakage power is 297.4nW, delay is 20.92ns and SNR is 4.77dB. This result performs on the cadence virtuoso tool at 45nm technology.

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