Reversible Logic Based Mapping of Quaternary Sequential Circuits

Reversible Logic Based Mapping of Quaternary Sequential Circuits Using QGFSOP Expression


Quaternary encoded binary circuits are more compact than their binary counterpart. Although several methods for designing binary reversible sequential circuits are presented, to the best of our knowledge, no design method for quaternary reversible sequential circuits has yet been reported in the literature. In this paper, we propose a design method for quaternary sequential circuits where the present state outputs are directly fedback to the next state determination circuit and that circuit is realized using QGFSOP expression as a cascade of one-digit, M-S, Feynman, and Toffoli gates. We also develop methods for making the sequential circuit falling-edge triggered and presettable using a quaternary Fred kin gate. As design examples, we present designs for up/down counters and universal registers. As there are no previous designs of quaternary sequential circuits, the closest comparison is made with designs of two-digit quaternary counter and universal register with designs of equivalent four-bit binary counter and universal register, respectively. In comparison to the equivalent binary designs, the proposed method requires less ancilla inputs with an increase in quantum cost.


Comments are closed.