December 11, 2017
Comments Off on Reversible Logic Based Mapping of Quaternary Sequential Circuits
Posted in: IEEE 2017, VLSI
Reversible Logic Based Mapping of Quaternary Sequential Circuits Using QGFSOP Expression Abstract: Quaternary encoded binary circuits are more compact than their binary counterpart. Although several methods for designing binary reversible sequential circuits are presented, to the best of our knowledge, no design method for quaternary reversible sequential circuits has yet been reported in the literature. In […]
December 11, 2017
Comments Off on Reducing RMS Noise in CMOS dynamic reconfigurable latched comparator in 50 nm
Posted in: IEEE 2017, VLSI
Reducing RMS Noise in CMOS dynamic reconfigurable latched comparator in 50 nm Abstract: This paper presents a new dynamic reconfigurable CMOS latched comparator that demonstrates low RMS noise, low offset and high gain. In this dynamic comparator circuit we make an independent inputs transistor and its input inverter circuit PMOS connected to clk1 with tail […]