Low Power Reconfigurable Hilbert Transformer Design with Row Bypassing Multiplier on FPGA

Low Power Reconfigurable Hilbert Transformer Design with Row Bypassing Multiplier on FPGA


Reconfigurability and low power have always been the main concern for the efficient filter implementation. This paper introduces two new low power and high speed reconfigurable Hilbert transformer designs. These designs are based on the carry save adder (CSA) and ripple carry adder (RCA) based row bypassing multipliers. The primary power reduction is procured by turning off adders when the multiplier operands are zero. In addition, the proposed Hilbert transformers are implemented with parallel architecture of multipliers to shorten the delay time. The proposed designs can be dynamically reconfigured with arbitrary coefficients that are only limited by their length and word size. These Hilbert transformers have been implemented and tested on Vertex-IV field programmable gate array (FPGA) board. The effectiveness of the proposed design method is presented with an example. The performance of both the designs is evaluated in terms of area (number of slices), speed, i.e., maximum frequency and power consumption. The results depict that the CSA row bypassing multiplier based Hilbert transformer achieves 17% increase in speed and 13% area reduction in comparison with RCA row bypassing multiplier based Hilbert transformer. While the power dissipation of the later transformer is 65% less than the former one.


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