December 11, 2017
Comments Off on Low-Power Split-Radix FFT Processors Using Radix-2 Butterfly Units
Posted in: IEEE 2017, VLSI
Low-Power Split-Radix FFT Processors Using Radix-2 Butterfly Units Abstract: Split-radix fast Fourier transform (SRFFT) is an ideal candidate for the implementation of a low-power FFT processor, because it has the lowest number of arithmetic operations among all the FFT algorithms. In the design of such processors, an efficient addressing scheme for FFT data as well […]
December 11, 2017
Comments Off on High-Speed, Low-Power, and Highly Reliable Frequency Multiplier for DLL-Based Clock Generator
Posted in: IEEE 2017, VLSI
High-Speed, Low-Power, and Highly Reliable Frequency Multiplier for DLL-Based Clock Generator Abstract: A high-speed, low-power, and highly reliable frequency multiplier is proposed for a delay-locked loop-based clock generator to generate a multiplied clock with a high frequency and wide frequency range. The proposed edge combiner achieves a high-speed and highly reliable operation using a hierarchical […]