December 11, 2017
Comments Off on A Parallel Decimal Multiplier Using Hybrid Binary Coded Decimal (BCD) Codes
Posted in: IEEE 2017, VLSI
A Parallel Decimal Multiplier Using Hybrid Binary Coded Decimal (BCD) Codes Abstract: A parallel decimal multiplier is proposed in this paper to improve performance by mainly exploiting the properties of three different binary coded decimal (BCD) codes, namely the redundant BCD excess-3 code (XS-3), the overloaded decimal digit set (ODDS) code and BCD-4221/5211 code, hence […]
December 11, 2017
Comments Off on A 28 nm Configurable Memory (TCAMBCAMSRAM) Using Push-Rule 6T BitCell Enabling Logic-in-Memory
Posted in: IEEE 2017, VLSI
A 28 nm Configurable Memory (TCAM/BCAM/SRAM) Using Push-Rule 6T BitCell Enabling Logic-in-Memory Abstract: Conventional content addressable memory (BCAM and TCAM) uses specialized 10T/16T bit cells that are significantly larger than 6T SRAM cells. A new BCAM/TCAM is proposed that can operate with standard push-rule 6T SRAM cells, reducing array area by 2-5× and allowing reconfiguration […]