December 11, 2017
Comments Off on Design of high speed multiplier using Modified Booth Algorithm with hybrid carry look-ahead adder
Posted in: IEEE 2017, VLSI
Design of high speed multiplier using Modified Booth Algorithm with hybrid carry look-ahead adder Abstract: In this paper novel method for multiplier and accumulator is proposed by combining reversible logic functions and hybrid carry look-ahead adder. Modified booth algorithm produces less delay in comparison with a normal multiplication process and it also moderates the number […]
December 11, 2017
Comments Off on Design for Testability of Sleep Convention Logic
Posted in: IEEE 2017, VLSI
Design for Testability of Sleep Convention Logic Abstract: Testability is a major concern in industry for today’s complex system-on-chip design. Design-for-testability (DFT) techniques are essential for any logic style, including asynchronous logic styles in order to reduce the test cost. Sleep convention logic (SCL) is a new promising asynchronous logic style that is based on […]