December 11, 2017
Comments Off on A 28 nm Configurable Memory (TCAMBCAMSRAM) Using Push-Rule 6T BitCell Enabling Logic-in-Memory
Posted in: IEEE 2017, VLSI
A 28 nm Configurable Memory (TCAM/BCAM/SRAM) Using Push-Rule 6T BitCell Enabling Logic-in-Memory Abstract: Conventional content addressable memory (BCAM and TCAM) uses specialized 10T/16T bit cells that are significantly larger than 6T SRAM cells. A new BCAM/TCAM is proposed that can operate with standard push-rule 6T SRAM cells, reducing array area by 2-5× and allowing reconfiguration […]
December 11, 2017
Comments Off on Low-Power Split-Radix FFT Processors Using Radix-2 Butterfly Units
Posted in: IEEE 2017, VLSI
Low-Power Split-Radix FFT Processors Using Radix-2 Butterfly Units Abstract: Split-radix fast Fourier transform (SRFFT) is an ideal candidate for the implementation of a low-power FFT processor, because it has the lowest number of arithmetic operations among all the FFT algorithms. In the design of such processors, an efficient addressing scheme for FFT data as well […]