December 11, 2017
Comments Off on A Pre-Optimization Technique to Generate Initial Reversible Circuits with Low Quantum Cost
Posted in: IEEE 2017, VLSI
A Pre-Optimization Technique to Generate Initial Reversible Circuits with Low Quantum Cost Abstract: In order to generate an initial reversible/quantum circuit to realize a given Boolean function, one of the major approaches is to find a small Exclusive-or Sum-Of-Products (ESOP) expression for the function; each product term in the ESOP expression naturally corresponds to a […]
December 11, 2017
Comments Off on A Parallel Decimal Multiplier Using Hybrid Binary Coded Decimal (BCD) Codes
Posted in: IEEE 2017, VLSI
A Parallel Decimal Multiplier Using Hybrid Binary Coded Decimal (BCD) Codes Abstract: A parallel decimal multiplier is proposed in this paper to improve performance by mainly exploiting the properties of three different binary coded decimal (BCD) codes, namely the redundant BCD excess-3 code (XS-3), the overloaded decimal digit set (ODDS) code and BCD-4221/5211 code, hence […]