Design for Testability of Sleep Convention Logic

Design for Testability of Sleep Convention Logic Abstract: Testability is a major concern in industry for today’s complex system-on-chip design. Design-for-testability (DFT) techniques are essential for any logic style, including asynchronous logic styles in order to reduce the test cost. Sleep convention logic (SCL) is a new promising asynchronous logic style that is based on […]


An Efficient Approach to Design a Compact Reversible Programmable Logic Array

An Efficient Approach to Design a Compact Reversible Programmable Logic Array  Abstract: Reversibility of logic module has eminent application in low power CMOS design, quantum computing, nanotechnology and optical computing. On the other hand, configurability of PLDs (Programmable Logic Devices) reduces NRE (Nonrecurring engineering) cost and makes faster design process that offers customer a wide […]