December 11, 2017
Comments Off on Design of Low Power, High Performance 2-4 and 4-16 Mixed-Logic Line Decoders
Posted in: IEEE 2017, VLSI
Design of Low Power, High Performance 2-4 and 4-16 Mixed-Logic Line Decoders Abstract: This paper introduces a mixed-logic design method for line decoders, combining transmission gate logic, pass transistor dual-value logic and static CMOS. Two novel topologies are presented for the 2-4 decoder: a 14-transistor topology aiming on minimizing transistor count and power dissipation and […]
December 11, 2017
Comments Off on Design of high speed multiplier using Modified Booth Algorithm with hybrid carry look-ahead adder
Posted in: IEEE 2017, VLSI
Design of high speed multiplier using Modified Booth Algorithm with hybrid carry look-ahead adder Abstract: In this paper novel method for multiplier and accumulator is proposed by combining reversible logic functions and hybrid carry look-ahead adder. Modified booth algorithm produces less delay in comparison with a normal multiplication process and it also moderates the number […]