December 11, 2017
Comments Off on Design of Reversible 32-Bit BCD Add-Subtract Unit using Parallel Pipelined Method
Posted in: IEEE 2017, VLSI
Design of Reversible 32-Bit BCD Add-Subtract Unit using Parallel Pipelined Method Abstract: Arithmetic unit design using reversible logic gate has received much attention as it reduces power dissipation with no loss of information. This paper proposes the design of 32-bit Binary Coded Decimal (BCD) addition and subtraction unit using reversible logic gates. The reversible 32 […]
December 11, 2017
Comments Off on Design of Register File using Reversible Logic
Posted in: IEEE 2017, VLSI
Design of Register File using Reversible Logic Abstract: Register file is the paramount aspect in computer memory unit. Eight bits (one memory unit) results in a single register and 32 of such register make up a register file. In this paper w e have presented the design of a complete register file using reversible logic […]