December 11, 2017
Comments Off on Modeling of Adders using CMOS and GDI Logic for Multiplier Applications
Posted in: IEEE 2017, VLSI
Modeling of Adders using CMOS and GDI Logic for Multiplier Applications Abstract: As the days go by, the innovation in the technology is growing faster and smaller chips with more complexity in the design and implementation. Design of adders is prime importance in any given embedded application; hence the design of reliable and efficient adder […]
December 11, 2017
Comments Off on Low-Quantum Cost Circuit Constructions for Adder and Symmetric Boolean Functions
Posted in: IEEE 2017, VLSI
Low-Quantum Cost Circuit Constructions for Adder and Symmetric Boolean Functions Abstract: Quantum computing necessitates the design of circuits via reversible logic gates. Efficient reversible circuit can be constructed by achieving low ancilla count, reducing logical depth and lowering Quantum costs. Generalized Peres gates have recently been realized with very low Quantum Cost (QC) by utilizing […]