December 11, 2017
Comments Off on Enhanced Built-In Self-Repair Techniques for Improving Fabrication Yield and Reliability of Embedded Memories
Posted in: IEEE 2017, VLSI
Enhanced Built-In Self-Repair Techniques for Improving Fabrication Yield and Reliability of Embedded Memories Abstract Error correction code (ECC) and built-in self-repair (BISR) techniques by using redundancies have been widely used for improving the yield and reliability of embedded memories. The target faults of these two schemes are soft errors and permanent (hard) faults, respectively. In recent works, there are also some techniques integrating ECC and BISR to deal with soft […]
December 11, 2017
Comments Off on Detector for MLC NAND Flash Memory Using Neighbor-A-Priori Information
Posted in: IEEE 2017, VLSI
Detector for MLC NAND Flash Memory Using Neighbor-A-Priori Information Abstract Cell-to-cell interference (CCI), arising from parasitic coupling-capacitance between adjacent cells, is a major factor for the degradation of cell threshold voltage in today’s flash memory chips. In this paper, three novel postprocessing detection schemes that exploit the a priori information of neighboring/interfering cells for mitigating the CCI effect in multilevel cell NAND flash memory are […]