December 11, 2017
Comments Off on Design-Efficient Approximate Multiplication Circuits Through Partial Product Perforation
Posted in: IEEE 2017, VLSI
Design-Efficient Approximate Multiplication Circuits Through Partial Product Perforation Abstract: Approximate computing has received significant attention as a promising strategy to decrease power consumption of inherently error tolerant applications. In this paper, we focus on hardware-level approximation by introducing the partial product perforation technique for designing approximate multiplication circuits. We prove in a mathematically rigorous manner […]
December 11, 2017
Comments Off on A New Paradigm of Common Sub expression Elimination by Unification of Addition and Subtraction
Posted in: IEEE 2017, VLSI
A New Paradigm of Common Subexpression Elimination by Unification of Addition and Subtraction Abstract: This paper makes a paradigm shift in the assumed notion of common subexpressions for complexity reduction of multiple constant multiplications implementation. Our proposed unified adder/subtractor (UAS)-based common subexpression elimination (CSE) algorithm is inspired by the recent advancement in complex arithmetic component […]