December 11, 2017
Comments Off on A Scalable Approximate DCT Architectures for Efficient HEVC Compliant Video Coding
Posted in: IEEE 2017, VLSI
A Scalable Approximate DCT Architectures for Efficient HEVC Compliant Video Coding Abstract: An approximate kernel for the discrete cosine transform (DCT) of length 4 is derived from the 4point DCT defined by the High Efficiency Video Coding (HEVC) standard, and used that for the computation of DCT and inverse DCT (IDCT) of powerof2 lengths. There […]
December 11, 2017
Comments Off on High-Performance Pipelined Architecture of Elliptic Curve Scalar Multiplication Over GF(2m)
Posted in: IEEE 2017, VLSI
High-Performance Pipelined Architecture of Elliptic Curve Scalar Multiplication Over GF(2m) Abstract: A high performance architecture of elliptic curve scalar multiplication based on the Montgomery ladder method over finite field GF(2m) is proposed. A pseudo-pipelined word serial finite field multiplier with word size w, suitable for the scalar multiplication is also developed. Implemented in hardware, this […]