December 11, 2017
Comments Off on A New Fast and Area-Efficient Adder-Based Sign Detector for RNS {2n- 1, 2n, 2n+ 1}
Posted in: IEEE 2017, VLSI
A New Fast and Area-Efficient Adder-Based Sign Detector for RNS { 2n−1,2n,2n+1 } Abstract: The moduli set {2n – 1, 2n, 2n + 1} has been widely used in residue number system (RNS)-based computations. Its sign extraction problem, albeit fundamentally important in magnitude comparison and other difficult algorithms in RNS, has received considerably less attention than its scaling and […]
December 11, 2017
Comments Off on A Low-Cost Low-Power Ring Oscillator-based Truly Random Number Generator for Encryption on Smart Cards
Posted in: IEEE 2017, VLSI
A Low-Cost Low-Power Ring Oscillator-Based Truly Random Number Generator for Encryption on Smart Cards Abstract: The design of a low-cost low-power ring oscillator-based truly random number generator (TRNG) macrocell, which is suitable to be integrated in smart cards, is presented. The oscillator sampling technique is exploited, and a tetrahedral oscillator with large jitter has been […]