December 11, 2017
Comments Off on Low-Power Variation-Tolerant Nonvolatile Lookup Table Design
Posted in: IEEE 2017, VLSI
Low-Power Variation-Tolerant Nonvolatile Lookup Table Design Abstract: Emerging nonvolatile memories (NVMs), such as MRAM, PRAM, and RRAM, have been widely investigated to replace SRAM as the configuration bits in field-programmable gate arrays (FPGAs) for high security and instant power ON. However, the variations inherent in NVMs and advanced logic process bring reliability issue to FPGAs. […]
December 11, 2017
Comments Off on A High-Throughput Energy-Efficient Implementation of Successive Cancellation Decoder for Polar Codes Using Combinational Logic
Posted in: IEEE 2017, VLSI
A High-Throughput Energy-Efficient Implementation of Successive Cancellation Decoder for Polar Codes Using Combinational Logic Abstract: This paper proposes a high-throughput energy-efficient Successive Cancellation (SC) decoder architecture for polar codes based on combinational logic. The proposed combinational architecture operates at relatively low clock frequencies compared to sequential circuits, but takes advantage of the high degree of parallelism […]