December 11, 2017
Comments Off on A 32 BIT MAC unit design using Vedic multiplier and reversible logic gate
Posted in: IEEE 2017, VLSI
A 32 BIT MAC unit design using Vedic multiplier and reversible logic gate Abstract: The Vedic Multiplier and the Reversible Logic Gates has Designed and implemented in the multiply and Accumulate Unit (MAC) and that is shown in this paper. A Vedic multiplier is designed by using Urdhava Triyagbhayam sutra and the adder design […]
December 11, 2017
Comments Off on Accelerated Accurate Timing Yield Estimation Based on Control Variates and Importance Sampling
Posted in: IEEE 2017, VLSI
Accelerated Accurate Timing Yield Estimation Based on Control Variates and Importance Sampling Abstract: Extensive research has been conducted on a statistical timing analysis of digital integrated circuits in the existence of statistical parameter variations. However, the proposed methods either lack accuracy or efficiency, which avoids coming up with an industry standard tool. Despite this fact, […]