Reducing RMS Noise in CMOS dynamic reconfigurable latched comparator in 50 nm

Reducing RMS Noise in CMOS dynamic reconfigurable latched comparator in 50 nm

 Abstract:

This paper presents a new dynamic reconfigurable CMOS latched comparator that demonstrates low RMS noise, low offset and high gain. In this dynamic comparator circuit we make an independent inputs transistor and its input inverter circuit PMOS connected to clk1 with tail transistor. The proposed comparator circuit shows better RMS noise response i.e. 704.38μV as compare to previous comparator circuit i.e. 1.1208mV and better output driving capacity as compare to conventional comparator circuit. The proposed comparator is simulated and implemented in LT SPICE 50nm technology.

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