Real-Time I/O Management System with COTS Peripherals

INTRODUCTION
INTEGRATING high-speed Commercial-Off-The-Shelf (COTS) peripherals within a real-time system offers substantial benefits in terms of cost reduction, time-tomarket and overall performance. Due to mass production, COTS components are significantly cheaper to produce than their application-specific peers. Since COTS components are already designed, a system’s time-to-market can be reduced by reusing existing components instead of creating new ones. Additionally, overall performance of mass produced components is often significantly higher than custom-made systems. For example, a PCI Express 1.0 bus [1] can transfer
data three orders of magnitude faster than the real-time SAFEbus [2]. However, the main challenge when integrating COTS peripherals within a real-time system is the unpredictable timing of the I/O subsystem since COTS components are typically designed paying little or no attention to worst case timing behaviors. In particular, we are concerned with I/O subsystems with high bandwidth requirements; a modern real-time system such as a search and rescue helicopter [3] may include several high-bandwidth components such as a Doppler navigation system, a forward look-ahead infrared radar, a night vision system,
and several types of communication systems. Modern I/O components such as these can inject significant traffic onto the I/O bus. For example, a single real time high-definition video may consume an I/O bandwidth of tens to hundreds of Mbps [4]. While priority-based real-time scheduling is a standard practice for CPU task scheduling, it is currently not supported by COTS peripherals and interconnect systems (e.g., PCI bus [1]). Due to the lack of real-time prioritization, data I/O transactions traveling through the COTS bus into or out of main memory can suffer unpredictable delay and cause deadline misses [5]. Similarly, when a COTS device is shared among multiple tasks, transactions requested by critical tasks cannot be prioritized and might be significantly delayed by other requests coming from low priority tasks. Unfortunately, end-to-end real-time guarantees cannot be achieved unless both tasks and I/O data transactions are properly processed in a prioritized manner. We address this challenge by introducing a real-time I/O management system that supports a wide range of priority-based scheduling policies, retains backward compatibility with existing COTS-based components, and achieves high realtime bus utilization without degrading peripherals’ throughput. The proposed framework acts like a “transparent layer” that does not add any additional burden at the user level, except for:

management system is completely transparent to main CPU
applications: in fact, through our real-time I/O management
system prototype, we were able to export to the
operating system two virtual network interfaces from a
single network device and use them without any user-end
application modifications.
The paper is organized as follows: First, we start with
related work in Section 2. In Section 3, we elaborate on the
design of the proposed real-time I/O management system.
This system, transparent to end-user CPU applications,
introduces two new types of components into the COTS
system, real-time bridges and a peripheral scheduler, to
provide temporal isolation on the COTS bus. In Section 4, we
elaborate on our Real-Time Calculus-based delay and buffer
size analysis. Using physical hardware, we then demonstrate
in Section 5 that timing violations can occur without our realtime
I/O management system, but with our system in place,
we can prevent I/O deadline misses. We finish with
conclusions and future directions in Section 6.
2 RELATED WORK
This paper significantly extends the work presented in one
of our previous conference papers [7]. In particular, we
designed a new real-time bridge with support for I/O
device virtualization that allows a priority driven device
sharing. The new design, which allows individual devices
to be properly shared among tasks with different real-time
criticalities, increases peripherals utilization and system
scalability (reducing the number of physical devices
needed). To validate our theory, we also developed a new
flow analysis and realized an improved real-time bridge
prototype based on a faster Power-PC processor (compared
with the Microblaze processor in our previous work), in
order to enable software-based flow partitioning. Using this
prototype, we performed new experiments showing how
we can now avoid possible deadline misses, in case of
device sharing.
In earlier work, Pellizzoni et al. proposed a coscheduling
framework between CPU and I/O peripherals to guarantee
main memory latency for tasks running on the CPU [8], [9].
The authors proposed to use passive Peripheral gate (P-gate)
devices to block and unblock peripherals (possibly reducing
I/O throughput and causing internal peripheral buffers to
overflow) and to synchronize I/O activity with tasks
executing on the CPU. Although this technique was effective
for predicting each task’s worst-case execution time (WCET)
in spite of I/O traffic spikes, it did not guarantee the
timeliness of I/O traffic. To the best of our knowledge, the
proposed real-time I/O management system provides
significant advancement over the current state of the art.
In fact, while it remains compatible with the cited timing
analysis to guarantee main memory latency for tasks
running on the CPU, the real-time I/O management system
provides the following novel features: 1) it identifies
different I/O flows within a COTS peripheral and enforces
predictable bandwidth reservations for each of them, 2) it
does not require synchronization between the CPU scheduler
and the I/O subsystem, and 3) it allows lossless
reshaping (under given assumptions) of bursty traffic from a
network of distributed real-time nodes.
Several papers in the literature address the problem of
interference among system components for access to main
memory. Empirical approaches can estimate the impact of
PCI-bus load on task computation time based on experimental
measurements of reference tasks [10]. Alternatively,
analytical approaches exist to bound I/O interference [9],
[11]. Analyses also exist to estimate the impact of mutual
interference among processing cores. For example, static
analysis can compute cache access delays in a multiprocessor
system [12], [13]. However, these results focus on deriving
the increase in task execution time while neglecting the effect
of delay on communication flows. Modeling complex COTS
interconnections and estimating delay and buffer requirements
for peripheral flows can be done in an AADL-based
environment [5]. An event-based model may be used to
estimate delay for both computation and communication
activities in a multicore system-on-chip (SOC) [14]. However,
lack of precise knowledge of COTS behavior implies
supporting I/O device virtualization techniques in order to schedule multiple real-time I/O flows within the same peripheral and realize a safe device
sharing among tasks with different priorities;
assigning a certain priority to each real-time I/O flow. In light of the discussed problems, the main contributions of this work are:
the design of a real-time I/O management system that supports (in a transparent and backward compatible manner) a wide range of priority-based scheduling
policies for COTS interconnect components;
. the extension of I/O device virtualization techniques to allow priority-based peripheral sharing;
. an extension of Real-Time Calculus theory [6] to determine the I/O delay bounds and each bridge’s necessary buffer size to guarantee lossless I/O traffic delivery; and
. a working prototype whose experimental measurements validate the effectiveness of proposed realtime I/O management system.
It is worth noticing that the proposed real-time I/O management system is completely transparent to main CPU
applications: in fact, through our real-time I/O management system prototype, we were able to export to the operating system two virtual network interfaces from a single network device and use them without any user-end
application modifications
.The paper is organized as follows: First, we start with related work in Section 2. In Section 3, we elaborate on the
design of the proposed real-time I/O management system. This system, transparent to end-user CPU applications,
introduces two new types of components into the COTS system, real-time bridges and a peripheral scheduler, to
provide temporal isolation on the COTS bus. In Section 4, we elaborate on our Real-Time Calculus-based delay and buffer
size analysis. Using physical hardware, we then demonstrate in Section 5 that timing violations can occur without our realtime
I/O management system, but with our system in place, we can prevent I/O deadline misses.

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