Modeling of Adders using CMOS and GDI Logic for Multiplier Applications

Modeling of Adders using CMOS and GDI Logic for Multiplier Applications

 Abstract:

As the days go by, the innovation in the technology is growing faster and smaller chips with more complexity in the design and implementation. Design of adders is prime importance in any given embedded application; hence the design of reliable and efficient adder on a VLSI based embedded application matters. In this paper we primarily deal with the construction of high speed adder circuits. Design and modeling of various adders like Ripple Carry Adder, Kogge Stone Adder, and Brent Kung Adder is done by using CMOS and GDI logic and comparative analysis is coated. The simulated results verify the functionality of high speed adders and performance parameters like Power, Delay and power-delay product is analyzed. With the results obtained and analysis made, gives a clear picture that KSA is the more efficient in speed and power parameters.

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