Logic Debugging of Arithmetic Circuits

   December 11, 2017    Comments Off on Logic Debugging of Arithmetic Circuits    Posted in: IEEE 2017, VLSI

Logic Debugging of Arithmetic Circuits

Abstract:

This paper presents a novel diagnosis and logic debugging method for gate-level arithmetic circuits. It detects logic bugs in a synthesized circuit caused by using a wrong gate (“gate replacement” error), which change the functionality of the circuit. The method is based on modeling the circuit in an algebraic domain and computing its algebraic “signature”. The location and type of the bug is determined by comparing signatures computed in both directions, using forward (PI to PO) and backward (PO to PI) rewriting. It will also perform automatic correction for the detected bugs. The approach is demonstrated and tested on a set of integer combinational arithmetic circuits.

 

  

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