Design And Development of Efficient Reversible Floating Point Arithmetic unit

Design And Development of Efficient Reversible Floating Point Arithmetic unit

Abstract:

For calculation or representation of very large or small numbers, large range is essential. These values can be represented using the IEEE-754 standard based floating point arithmetic representation. The paper presents efficient approach towards designing of high speed floating point unit using reversible logic. Programmable reversible logic design is trending as a prospective logic design style for implementation in recent nanotechnology and quantum computing with low impact on circuit heat generation. There are various reversible implementations of logical and arithmetic units have been proposed in the existing research, but very few reversible floating-point designs has been designed. Floating-point operations are used very frequently in nearly all computing disciplines. The analysis of proposed reversible circuit can be done in terms of quantum cost, garbage outputs, constant inputs, power consumption, speed and area.

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