December 11, 2017
Comments Off on Index based Round Robin Arbiter for NoC Routers
Posted in: IEEE 2017, VLSI
Index-based Round-Robin Arbiter for NoC Routers Abstract: Scalable on-chip communication system such as Network-on-Chip (NoC) is needed to meet the communication demand of large number of SoC (System on Chip) cores. In the NoC router micro-architecture design, arbiter has become increasingly important due to its significant impact on the performance and efficiency of NoC systems. […]
December 11, 2017
Comments Off on Implementation of Testable Reversible Sequential Circuit on FPGA
Posted in: IEEE 2017, VLSI
Implementation of Testable Reversible Sequential Circuit on FPGA Abstract: The design of testable sequential circuits by two vectors using conservative logic. The proposed sequential circuits based on conservative logic outclass the traditional sequential circuits built using classical gates in terms of testability. Any sequential circuits based on conservative logic can test for stuck-at 0 and […]