December 11, 2017
Comments Off on Low-Complexity Tree Architecture for Finding the First Two Minima
Posted in: IEEE 2017, VLSI
Low-Complexity Tree Architecture for Finding the First Two Minima Abstract: This brief presents an area-efficient tree architecture for finding the first two minima as well as the index of the first minimum, which is essential in the design of a low-density parity-check decoder based on the min-sum algorithm. The proposed architecture reduces the number of […]
December 11, 2017
Comments Off on Logic Debugging of Arithmetic Circuits
Posted in: IEEE 2017, VLSI
Logic Debugging of Arithmetic Circuits Abstract: This paper presents a novel diagnosis and logic debugging method for gate-level arithmetic circuits. It detects logic bugs in a synthesized circuit caused by using a wrong gate (“gate replacement” error), which change the functionality of the circuit. The method is based on modeling the circuit in an algebraic […]