December 11, 2017
Comments Off on Modeling CMOS Gates Using Equivalent Inverters
Posted in: IEEE 2017, VLSI
Modeling CMOS Gates Using Equivalent Inverters Abstract: In this paper a complete approach for timing and power modeling and characterization of the CMOS gates is proposed. At first, a simplified but still accurate transistor current model is proposed taking into account the nanoscale effects which have a countable effect on the circuit behavior. Using the […]
December 11, 2017
Comments Off on Low-Power and Area-Efficient Shift Register Using Pulsed Latches
Posted in: IEEE 2017, VLSI
Low-Power and Area-Efficient Shift Register Using Pulsed Latches Abstract: This paper proposes a low-power and area-efficient shift register using pulsed latches. The area and power consumption are reduced by replacing flip-flops with pulsed latches. This method solves the timing problem between pulsed latches through the use of multiple non-overlap delayed pulsed clock signals instead of […]