December 11, 2017
Comments Off on Design of Register File using Reversible Logic
Posted in: IEEE 2017, VLSI
Design of Register File using Reversible Logic Abstract: Register file is the paramount aspect in computer memory unit. Eight bits (one memory unit) results in a single register and 32 of such register make up a register file. In this paper w e have presented the design of a complete register file using reversible logic […]
December 11, 2017
Comments Off on Design of Low Power, High Performance 2-4 and 4-16 Mixed-Logic Line Decoders
Posted in: IEEE 2017, VLSI
Design of Low Power, High Performance 2-4 and 4-16 Mixed-Logic Line Decoders Abstract: This paper introduces a mixed-logic design method for line decoders, combining transmission gate logic, pass transistor dual-value logic and static CMOS. Two novel topologies are presented for the 2-4 decoder: a 14-transistor topology aiming on minimizing transistor count and power dissipation and […]