December 11, 2017
Comments Off on Energy-Aware Scheduling of FIR Filter Structures using a Timed Automata Model
Posted in: IEEE 2017, VLSI
Energy-Aware Scheduling of FIR Filter Structures using a Timed Automata Model Abstract: Software Defined Radio (SDR) devices are becoming increasingly popular due to their support for mode-, standard- and application-flexibility. At the same time however, the energy consumption of such devices typically suffers from the use of reconfigurable real-time platforms which are known to be […]
December 11, 2017
Comments Off on Design of Reversible 32-Bit BCD Add-Subtract Unit using Parallel Pipelined Method
Posted in: IEEE 2017, VLSI
Design of Reversible 32-Bit BCD Add-Subtract Unit using Parallel Pipelined Method Abstract: Arithmetic unit design using reversible logic gate has received much attention as it reduces power dissipation with no loss of information. This paper proposes the design of 32-bit Binary Coded Decimal (BCD) addition and subtraction unit using reversible logic gates. The reversible 32 […]