December 11, 2017
Comments Off on Floating-Point Butterfly Architecture Based on Binary Signed-Digit Representation
Posted in: IEEE 2017, VLSI
Floating-Point Butterfly Architecture Based on Binary Signed-Digit Representation Abstract: Fast Fourier transform (FFT) coprocessor, having a significant impact on the performance of communication systems, has been a hot topic of research for many years. The FFT function consists of consecutive multiply add operations over complex numbers, dubbed as butterfly units. Applying floating-point (FP) arithmetic to […]
December 11, 2017
Comments Off on Exploiting Inherent Characteristics of Reversible Circuits for Faster Combinational Equivalence Checking
Posted in: IEEE 2017, VLSI
Exploiting Inherent Characteristics of Reversible Circuits for Faster Combinational Equivalence Checking Abstract: Reversible circuits implement invertible logic functions. They are of great interest to cryptography, coding theory, interconnect design, computer graphics, quantum computing, and many other fields. As for conventional circuits, checking the combinational equivalence of two reversible circuits is an important but difficult (coNP-complete) […]