December 11, 2017
Comments Off on Logic Synthesis in Reversible PLA
Posted in: IEEE 2017, VLSI
Logic Synthesis in Reversible PLA Abstract: Reversible logic have been motivated by consideration of zero-energy computation. Re-configurability and structural regularity of Programmable Logic Devices caused wide use of it by the logic designers. In this paper, we propose a design algorithm for a PLA (Programmable Logic Array) with a newly designed low cost 3 × […]
December 11, 2017
Comments Off on High-Speed and Energy-Efficient Carry Skip Adder Operating Under a Wide Range of Supply Voltage Levels
Posted in: IEEE 2017, VLSI
High-Speed and Energy-Efficient Carry Skip Adder Operating Under a Wide Range of Supply Voltage Levels Abstract: In this paper, we present a carry skip adder (CSKA) structure that has a higher speed yet lower energy consumption compared with the conventional one. The speed enhancement is achieved by applying concatenation and incrementation schemes to improve the […]