December 11, 2017
Comments Off on Low Power Multiplier Architectures Using Vedic Mathematics in 45nm Technology for High Speed Computing
Posted in: IEEE 2017, VLSI
Low Power Multiplier Architectures Using Vedic Mathematics in 45nm Technology for High Speed Computing Abstract: Speed and the overall performance of any digital signal processor are largely determined by the efficiency of the multiplier units present within. The use of Vedic mathematics has resulted in significant improvement in the performance of multiplier architectures used for […]
December 11, 2017
Comments Off on Low Power High Speed Area Efficient Error Tolerant Adder Using Gate Diffusion Input Method
Posted in: IEEE 2017, VLSI
Low Power High Speed Area Efficient Error Tolerant Adder Using Gate Diffusion Input Method Abstract: In digital VLSI circuits, perfectly accurate outputs are not always needed. So designers have started to design error tolerance circuits which provide good enough output for computation. On the basis of this fact, error tolerant adder (ETA) is designed which […]