December 11, 2017
Comments Off on Low-Quantum Cost Circuit Constructions for Adder and Symmetric Boolean Functions
Posted in: IEEE 2017, VLSI
Low-Quantum Cost Circuit Constructions for Adder and Symmetric Boolean Functions Abstract: Quantum computing necessitates the design of circuits via reversible logic gates. Efficient reversible circuit can be constructed by achieving low ancilla count, reducing logical depth and lowering Quantum costs. Generalized Peres gates have recently been realized with very low Quantum Cost (QC) by utilizing […]
December 11, 2017
Comments Off on Low Power Reconfigurable Hilbert Transformer Design with Row Bypassing Multiplier on FPGA
Posted in: IEEE 2017, VLSI
Low Power Reconfigurable Hilbert Transformer Design with Row Bypassing Multiplier on FPGA Abstract: Reconfigurability and low power have always been the main concern for the efficient filter implementation. This paper introduces two new low power and high speed reconfigurable Hilbert transformer designs. These designs are based on the carry save adder (CSA) and ripple carry adder […]