December 11, 2017
Comments Off on Pre-Encoded Multipliers Based on Non-Redundant Radix-4 Signed-Digit Encoding
Posted in: IEEE 2017, VLSI
Pre-Encoded Multipliers Based on Non-Redundant Radix-4 Signed-Digit Encoding Abstract: In this paper, we introduce an architecture of pre-encoded multipliers for digital signal processing applications based on off-line encoding of coefficients. To this extend, the Non-Redundant radix-4 Signed-Digit (NR4SD) encoding technique, which uses the digit values {−1,0,+1,+2} or {−2,−1,0,+1} , is proposed leading to a multiplier […]
December 11, 2017
Comments Off on Modeling of Adders using CMOS and GDI Logic for Multiplier Applications
Posted in: IEEE 2017, VLSI
Modeling of Adders using CMOS and GDI Logic for Multiplier Applications Abstract: As the days go by, the innovation in the technology is growing faster and smaller chips with more complexity in the design and implementation. Design of adders is prime importance in any given embedded application; hence the design of reliable and efficient adder […]