December 11, 2017
Comments Off on A Low-Voltage Radiation-Hardened 13T SRAM Bitcell for Ultralow Power Space Applications
Posted in: IEEE 2017, VLSI
A Low-Voltage Radiation-Hardened 13T SRAM Bitcell for Ultralow Power Space Applications Abstract: Continuous transistor scaling, coupled with the growing demand for low-voltage, low-power applications, increases the susceptibility of VLSI circuits to soft-errors, especially when exposed to extreme environmental conditions, such as those encountered by space applications. The most vulnerable of these circuits are memory arrays […]
December 11, 2017
Comments Off on Design Methodology for Voltage-Scaled Clock Distribution Networks
Posted in: IEEE 2017, VLSI
Design Methodology for Voltage-Scaled Clock Distribution Networks Abstract: A low-voltage/swing clocking methodology is developed through both circuit and algorithmic innovations. The primary objective is to significantly reduce the power consumed by the clock network while maintaining the circuit performance the same. The methodology consists of two primary components: a novel D-flip-flop (DFF) cell that maximizes […]