December 11, 2017
Comments Off on A 28-nm CMOS 1 V 3.5 GSs 6-bit DAC With Signal-Independent Delta-I Noise DfT Scheme
Posted in: IEEE 2017, VLSI
A 28-nm CMOS 1 V 3.5 GS/s 6-bit DAC With Signal-Independent Delta-I Noise DfT Scheme Abstract This paper presents a 3.5 GS/s 6-bit current-steering digital-to-analog converter (DAC) with auxiliary circuitry to assist testing in a 1 V digital 28-nm CMOS process. The DAC uses only thin-oxide transistors and occupies 0.035 mm2, making it suitable to embedding in VLSI systems, e.g., field-programmable gate array (FPGA). To cope with […]
December 11, 2017
Comments Off on 5-bit 5-GSs Non interleaved Time-Based ADC in 65-nm CMOS for Radio-Astronomy Applications M
Posted in: IEEE 2017, VLSI
5-bit 5-GS/s Noninterleaved Time-Based ADC in 65-nm CMOS for Radio-Astronomy Applications M Abstract This paper presents a 5-bit noninterleaved time-based analog-to-digital converter (ADC), which operates at a 5-GS/s rate. The ADC is designed for the use in radio-astronomy telescopes, for whichtime interleaving is not acceptable. The ADC employs a dynamic, differential voltage-to-time converter, a folded-flash time-to-digital converter (TDC), and calibration circuitry. To generate reference delays, the calibration circuitry utilizes a […]