December 11, 2017
Comments Off on Optimum pMOS-to-nMOS Width Ratio for Efficient Subthreshold CMOS Circuits
Posted in: IEEE 2017, VLSI
Optimum pMOS-to-nMOS Width Ratio for Efficient Subthreshold CMOS Circuits Abstract The subthreshold region of operation in digital CMOS circuits provides a suitable low-power solution for many applications that need tremendously low-energy operation. However, this advantage comes at the cost of speed, so enhancing the speed of subthreshold circuits can expand their application spectrum. This paper presents the optimum pMOS-to-nMOS width ratio that leads to the maximum frequency of operation in […]
December 11, 2017
Comments Off on Improving Convergence and Simulation Time of Quantum Hydrodynamic Simulation Application to Extraction of Best 10-nm Fin FET Parameter Values
Posted in: IEEE 2017, VLSI
Improving Convergence and Simulation Time of Quantum Hydrodynamic Simulation: Application to Extraction of Best 10-nm FinFET Parameter Values Abstract As electronic devices enter the deep nanometer regime, accurate and efficient device simulationsbecome necessary to account for the emerging quantum effects. The traditional drift-diffusion andhydrodynamic (HD) device simulation models are not accurate in this regime. It is important to use thequantum HD (QHD) simulation model. However, this model suffers […]