December 11, 2017
Comments Off on A New Paradigm of Common Sub expression Elimination by Unification of Addition and Subtraction
Posted in: IEEE 2017, VLSI
A New Paradigm of Common Subexpression Elimination by Unification of Addition and Subtraction Abstract: This paper makes a paradigm shift in the assumed notion of common subexpressions for complexity reduction of multiple constant multiplications implementation. Our proposed unified adder/subtractor (UAS)-based common subexpression elimination (CSE) algorithm is inspired by the recent advancement in complex arithmetic component […]
December 11, 2017
Comments Off on Utilization-Aware Self-Tuning Design for TLC Flash Storage Devices
Posted in: IEEE 2017, VLSI
Utilization-Aware Self-Tuning Design for TLC Flash Storage Devices Abstract The high-density, low-cost triple-level-cell (TLC) flash memory has gradually dominated the flashstorage market because of the fast-growing demand for storage capacity. However, the advances of manufacturing technologies also make TLC flash memory suffer serious performance degradation compared with the low-density, high-performance single-level-cell (SLC) flash memory. To address this issue, some vendors enable blocks of TLC flash memory to work as […]