December 11, 2017
Comments Off on High-Performance Pipelined Architecture of Elliptic Curve Scalar Multiplication Over GF(2m)
Posted in: IEEE 2017, VLSI
High-Performance Pipelined Architecture of Elliptic Curve Scalar Multiplication Over GF(2m) Abstract: A high performance architecture of elliptic curve scalar multiplication based on the Montgomery ladder method over finite field GF(2m) is proposed. A pseudo-pipelined word serial finite field multiplier with word size w, suitable for the scalar multiplication is also developed. Implemented in hardware, this […]
December 11, 2017
Comments Off on Design-Efficient Approximate Multiplication Circuits Through Partial Product Perforation
Posted in: IEEE 2017, VLSI
Design-Efficient Approximate Multiplication Circuits Through Partial Product Perforation Abstract: Approximate computing has received significant attention as a promising strategy to decrease power consumption of inherently error tolerant applications. In this paper, we focus on hardware-level approximation by introducing the partial product perforation technique for designing approximate multiplication circuits. We prove in a mathematically rigorous manner […]