December 11, 2017
Comments Off on A 1-16-Gbs All-Digital Clock and Data Recovery With a Wideband, High-Linearity Phase Interpolator
Posted in: IEEE 2017, VLSI
A 1-16-Gb/s All-Digital Clock and Data Recovery With a Wideband, High-Linearity Phase Interpolator Abstract: An all-digital phase interpolator (PI)-based clock and data recovery (CDR) is proposed in this paper to accommodate any data rate continuously from 1 to 16 Gb/s with quadrature sampling clocks from 4 to 8 GHz. A new, low-power and two-step PI […]
December 11, 2017
Comments Off on A New Fast and Area-Efficient Adder-Based Sign Detector for RNS {2n- 1, 2n, 2n+ 1}
Posted in: IEEE 2017, VLSI
A New Fast and Area-Efficient Adder-Based Sign Detector for RNS { 2n−1,2n,2n+1 } Abstract: The moduli set {2n – 1, 2n, 2n + 1} has been widely used in residue number system (RNS)-based computations. Its sign extraction problem, albeit fundamentally important in magnitude comparison and other difficult algorithms in RNS, has received considerably less attention than its scaling and […]