December 11, 2017
Comments Off on Thermal-Aware Small-Delay Defect Testing in Integrated Circuits for Mitigating Overkil
Posted in: IEEE 2017, VLSI
Thermal-Aware Small-Delay Defect Testing in Integrated Circuits for Mitigating Overkil Abstract: At-speed testing of deep-submicrometer or nano-scale integrated circuits (ICs) consumes excessive power and creates hotspots and temperature gradient in the chip-under-test. The problem worsens for 3-D ICs, where heat dissipation across layers is more unbalanced. These hotspots in a circuit often cause severe degradation […]
December 11, 2017
Comments Off on Low-Power Variation-Tolerant Nonvolatile Lookup Table Design
Posted in: IEEE 2017, VLSI
Low-Power Variation-Tolerant Nonvolatile Lookup Table Design Abstract: Emerging nonvolatile memories (NVMs), such as MRAM, PRAM, and RRAM, have been widely investigated to replace SRAM as the configuration bits in field-programmable gate arrays (FPGAs) for high security and instant power ON. However, the variations inherent in NVMs and advanced logic process bring reliability issue to FPGAs. […]