December 11, 2017
Comments Off on Accelerated Accurate Timing Yield Estimation Based on Control Variates and Importance Sampling
Posted in: IEEE 2017, VLSI
Accelerated Accurate Timing Yield Estimation Based on Control Variates and Importance Sampling Abstract: Extensive research has been conducted on a statistical timing analysis of digital integrated circuits in the existence of statistical parameter variations. However, the proposed methods either lack accuracy or efficiency, which avoids coming up with an industry standard tool. Despite this fact, […]
December 11, 2017
Comments Off on High-Throughput Finite Field Multipliers Using Redundant Basis for FPGA and ASIC Implementations
Posted in: IEEE 2017, VLSI
High-Throughput Finite Field Multipliers Using Redundant Basis for FPGA and ASIC Implementations Abstract: Redundant basis (RB) multipliers over Galois Field ( GF(2m)) have gained huge popularity in elliptic curve cryptography (ECC) mainly because of their negligible hardware cost for squaring and modular reduction. In this paper, we have proposed a novel recursive decomposition algorithm for […]