December 11, 2017
Comments Off on A Low-Power Hybrid RO PUF With Improved Thermal Stability for Lightweight Application
Posted in: IEEE 2017, VLSI
A Low-Power Hybrid RO PUF With Improved Thermal Stability for Lightweight Applications Abstract: Ring oscillator (RO)-based physical unclonable function (PUF) is resilient against noise impacts, but its response is susceptible to temperature variations. This paper presents a low-power and small footprint hybrid RO PUF with a very high temperature stability, which makes it an ideal […]
December 11, 2017
Comments Off on A 32 BIT MAC unit design using Vedic multiplier and reversible logic gate
Posted in: IEEE 2017, VLSI
A 32 BIT MAC unit design using Vedic multiplier and reversible logic gate Abstract: The Vedic Multiplier and the Reversible Logic Gates has Designed and implemented in the multiply and Accumulate Unit (MAC) and that is shown in this paper. A Vedic multiplier is designed by using Urdhava Triyagbhayam sutra and the adder design […]