December 11, 2017
Comments Off on Aging Aware Reliable Multiplier Design With Adaptive Hold Logic
Posted in: IEEE 2017, VLSI
Aging-Aware Reliable Multiplier Design With Adaptive Hold Logic Abstract: Digital multipliers are among the most critical arithmetic functional units. The overall performance of these systems depends on the throughput of the multiplier. Meanwhile, the negative bias temperature instability effect occurs when a pMOS transistor is under negative bias (Vgs = -Vdd), increasing the threshold voltage of […]
December 11, 2017
Comments Off on A Single Ended With Dynamic Feedback Control 8T Subthreshold SRAM Cell
Posted in: IEEE 2017, VLSI
A Single-Ended With Dynamic Feedback Control 8T Subthreshold SRAM Cell Abstract: A novel 8-transistor (8T) static random access memory cell with improved data stability in subthreshold operation is designed. The proposed single-ended with dynamic feedback control 8T static RAM (SRAM) cell enhances the static noise margin (SNM) for ultralow power supply. It achieves write SNM of […]