December 11, 2017
Comments Off on Design Study of a Low Power High Speed Full Adder Using GDI Multiplexer
Posted in: IEEE 2017, VLSI
Design & Study of a Low Power High Speed Full Adder Using GDI Multiplexer Abstract: This paper proposes a new method for implementing a low power full adder by means of a set of Gate Diffusion Input (GDI) cell based multiplexers. Full adder is a very common example of combinational circuits and is used widely in […]
December 11, 2017
Comments Off on Berger Check and Fault Tolerant Reversible Arithmetic Component Design
Posted in: IEEE 2017, VLSI
Berger Check and Fault Tolerant Reversible Arithmetic Component Design Abstract: In order to continue the revolution in the computer hardware performance, we need to reduce the energy dissipated in each logic operation. Energy dissipation can be reduced by preventing information loss. This is achieved by designing the circuits using reversible logic gates. It has wider […]