December 11, 2017
Comments Off on Design And Development of Efficient Reversible Floating Point Arithmetic unit
Posted in: IEEE 2017, VLSI
Design And Development of Efficient Reversible Floating Point Arithmetic unit Abstract: For calculation or representation of very large or small numbers, large range is essential. These values can be represented using the IEEE-754 standard based floating point arithmetic representation. The paper presents efficient approach towards designing of high speed floating point unit using reversible logic. […]
December 11, 2017
Comments Off on Design and Analysis of Approximate Compressors for Multiplication
Posted in: IEEE 2017, VLSI
Design and Analysis of Approximate Compressors for Multiplication Abstract: Inexact (or approximate) computing is an attractive paradigm for digital processing at nanometric scales. Inexact computing is particularly interesting for computer arithmetic designs. This paper deals with the analysis and design of two new approximate 4-2 compressors for utilization in a multiplier. These designs rely on different […]