December 11, 2017
Comments Off on Design and Implementation of Field Programmable Gate Array Based Error Tolerant Adder for Image Processing Application
Posted in: IEEE 2017, VLSI
Design and Implementation of Field Programmable Gate Array Based Error Tolerant Adder for Image Processing Application Abstract: In the era of low power, high performance digital systems are needed to boost up the technology revolution in nano-electronics. Realization of new digital logic is essential for making revolutionary changes in low power and high speed performance. […]
December 11, 2017
Comments Off on Design and Implementation of Arithmetic Logic Unit (ALU) Using Modified NovelBit Adder in QCA
Posted in: IEEE 2017, VLSI
Design and Implementation of Arithmetic Logic Unit (ALU) using Modified Novel Bit Adder in QCA Abstract: Moore’s law states that the number of transistors that could be integrated into a single die would grow exponentially with time. Thus this causes increasing computational complexity of the chip and physical limitations of devices such as power consumption, interconnect will […]